
Apple II Computer Info
You can't do ANYTHING - it turns off everything in the chip (all
interrupt sources, transmit and receive).
> o You cannot receive if the DCD signal is false.
You also cannot transmit if RTS is turned off.
> CONTROL REGISTER ($C08B + $n0)
> 4 - receiver clock source
> 0 = external receiver clock
Don't use this setting on the SSC - there is no external receiver clock.
> 3210 - internal baud rate generator
> 0 0 0 0 = external receiver clock x 16
Don't use this setting on the SSC - it only works if the ACIA is being
clocked by a square wave input, not a crystal.
> COMMAND REGISTER ($C08A + $n0)
> 32 - transmitter controls (RTS signal)
> 0 0 = transmit IRQ disabled, RTS high
That is "transmitter AND transmit IRQ disabled, RTS high"
> STATUS REGISTER ($C089 + $n0)
> 7 - IRQ pending status
> 0 = no interrupt
> 1 = interrupt has occurred
Be very careful when reading the status register with interrupts
enabled: if the IRQ bit is set, it is cleared by reading this
register. This means, for example, if you you are are using receive
interrupts but are polling the status register to detect when you can
next transmit a character, you may cause an IRQ to be lost if it
happens to be read by the transmit routine first.
To avoid this, you must check the IRQ flag whenever this register is
read.
This is really only a problem if you're relying on the IRQ
flag to detect an interrupt from the SSC - the interrupt will still
occur, but the interrupt handler will not see the IRQ flag set. If it
is a receive or transmit interrupt, there is a separate flag you can
check, but you cannot identify a state change interrupt for DCD or DSR
unless the IRQ bit is set. You can save the previous state for DCD
and DSR, but a three-way toggle on one of the lines may cause two
interrupts but go undetected.
--
David Empson
Snail mail: P.O. Box 27-103, Wellington, New Zealand
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Apple II Computer Technical Information : Apple II Family Hardware Info
ftp://ground.ecn.uiowa.edu/2/apple2/miscinfo/hardware : May 2001 : 483 of 572
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